An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies, 1982

The Mesa architecture is implemented on a variety of processors, and dynamic instruction frequency data for two programs is used to analyze the architecture in an implementation independent fashion. The Mesa compiler allocates variables in an order based upon their static frequency of use, and measurements are provided that show that these static predictions predict run time usage as well. We provide an evaluation of the advantages and costs of Mesa's compact byte encoding, its reliance upon an evaluation stack, and its use of memory. The Mesa language has evolved over time in a hardware environment oriented around 16-bit quantities with growing use of and accommodations to 32-bit quantifies. The cost of emulating 32-bit data paths on a 16-bit machine is identified for a program that heavily exploits longer values. Several potential areas for improving the execution speed of a Mesa processor with special purpose hardware are identified.